The present invention relates generally to the fabrication of integrated circuits and, more particularly, relates to the fabrication of integrated circuits by a patterning process which uses self-assembling polymers.
The semiconductor industry has a need to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large-scale integration has led to a continued shrinking of the circuit dimensions and features of the devices.
The ability to reduce the sizes of structures such as gates in field effect transistors (FETs), is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current commercial fabrication processes, optical devices expose the photoresist using light having a wavelength of 193 nm (nanometers). Research and development laboratories are experimenting with the EUV (13 nm) wavelength to reduce the size of structures. Further, advanced lithographic technologies are being developed that utilize immersion techniques to improve resolution.
One challenge facing lithographic technology is fabricating features having a critical dimension (CD) below 70 nm. All steps of the photolithographic techniques currently employed must be improved to achieve the further reduction in feature size.
In a conventional technique, light is exposed through a binary mask to a photoresist layer on a layer of material. The photoresist layer may be either a positive or a negative photoresist and can be a silicon-containing, dry-developed resist. In the case of a positive photoresist, the light causes a photochemical reaction in the photoresist. The photoresist is removable with a developer solution at the portions of the photoresist that are exposed through the mask. The photoresist is developed to clear away these portions, whereby a photoresist feature remains on the layer of material. An integrated circuit feature, such as a gate, via, or interconnect, is then etched into the layer of material, and the remaining photoresist is removed.
The linewidth of the integrated circuit feature is limited using the conventional process. For example, aberrations, focus, and proximity effects in the use of light limit the ability to fabricate features having reduced linewidth. Using a 248 nm wavelength light source, the minimum printed feature linewidth is between 300 and 150 nm, using conventional techniques. The most advanced lithography tools can now resolve to 100 nm feature size which be improved to 70 to 80 nm with immersion lithography. With IC design expected to require sub-50 nm interconnects, it is apparent that conventional lithography cannot meet this design requirement.
Accordingly there is a need for reducing the IC interconnect opening diameter to below the resolutions of the conventional lithographic tools, to improve circuit layout density.
It has been known that certain materials are capable of organizing into ordered patterns under certain desired conditions, which is typically referred to as the self-assembly of materials.
Self-assembling polymers are capable of self-organizing into nanometer-scale patterns, enabling future advances in semiconductor technology as shown for example in Nealey et al., “Self-assembling resists for nanolithography” Electron Devices Meeting. 2005. IEDM Technical Digest. IEEE International 5-7 Dec. 2005 Page(s):4 pp the disclosure in which is incorporated by reference herein, as described in this reference, each self-assembling polymer system typically contains two or more different polymeric block components that are immiscible with one another. Under suitable conditions, the two or more immiscible polymeric block components separate into two or more different phases on a nanometer scale and thereby form ordered patterns of isolated nano-sized structural units. Along the same lines, Edelstein et al. U.S. Patent Application Publication 2005/0167838, the disclosure of which is incorporated by reference herein, discloses the use of a self-assembled polymer pattern to form sub-lithographic features in an oxide.
Some, such as Babcock U.S. Pat. No. 6,630,404 and Krivokapic U.S. Pat. No. 6,534,399, the disclosures of which have been incorporated by reference herein, have proposed self-assembled monolayers to reduce feature size of a lithographically defined feature. The result is not a self-assembled pattern.
Others, such as Chen et al. U.S. Pat. No. 6,773,616, the disclosure of which has been incorporated by reference herein, have proposed self-assembled polymers to pattern a hard mask. There is no pattern registration with an underlying layer.
IBM Technical Disclosure Bulletin, “Self-Assembled monolayers as High-Resolution Resists, vol. 39, No. 04, p. 111, and IBM Technical Disclosure Bulletin, “Fabrication of Gold Nanostructures by Lithography with Self-Assembled Monolayers”, vol. 39, No. 12, p. 235, the disclosures of which are incorporated by reference herein, disclose forming self-assembled monolayers and then “writing” on them with a Scanning tunneling Microscope or ultraviolet light to form patterns.
Aizenberg et al. J1P2005033184, the disclosure of which is incorporated by reference herein, begins with a lithographically formed feature and then uses a self-assembled monomolecular film to form multiple sublithographic features within the lithographically-formed feature.
IC technology, however, requires precise placement or registration of individual structural units for formation of metal lines and vias in the wiring levels. Therefore, an ordered array of repeating structural units formed by self-assembling polymers could not be used in IC devices, because of lack of alignment or registration of the position of individual structure units.
Accordingly, it is an object of the present invention to use self-assembling polymers to form sublithographic features which are registered with a previously-defined lithographic pattern.
It is another object of the present invention to use self-assembling polymers which assemble upon annealing to form sublithographic features which are registered with a previously-defined lithographic pattern.
It is yet another object of the present invention to use block copolymers as the self-assembling polymers in the present invention.
These and other purposes of the present invention will become apparent after referring to the following description of the invention considered in conjunction with the accompanying figures.